发明名称 WIRING FORMATION METHOD
摘要 PURPOSE:To form a flat plug part when etching back a W layer (Blk-W layer) which is laminated on an adhesive layer by CVD method. CONSTITUTION:After a nitride layer 18 is formed on a surface of an SiO2 layer insulating film 17 by carrying out lamp annealing in NH3 atmosphere in a manufacturing process of a MOS-FET, contact holes 19, 20 are opened and an adhesive layer 23 is formed of a Ti layer 21 and a TiNX layer 22. When forming a following Blk-W layer (not illustrated in the figures), a wafer is heated at a high temperature; however, the nitride layer 18 blocks oxygen from the SiO2 layer insulating film 17 and prevents oxidation of a Ti layer 21. Since residue of Ti oxide does not remain when the adhesive layer 23 is etched back and an over etching time is reduced, it is possible to prevent erosion of the adhesive layer 23 inside the contact holes 19, 20 due to loading effect.
申请公布号 JPH05144951(A) 申请公布日期 1993.06.11
申请号 JP19910275066 申请日期 1991.09.27
申请人 SONY CORP 发明人 SATO JUNICHI;MIYAMOTO TAKAAKI
分类号 H01L21/28;H01L21/318;H01L21/3205;H01L21/3213;H01L21/768;H01L23/522 主分类号 H01L21/28
代理机构 代理人
主权项
地址
您可能感兴趣的专利