发明名称 OUT OF CLOCK SYNCHRONISM DETECTING CIRCUIT
摘要 <p>PURPOSE:To detect out of synchronizing stably at all time by avoiding mis- detection of out of synchronism caused by the deterioration of the C/N of reception data or the like without use of a low pass filter requiring adjustment of a cut-off frequency. CONSTITUTION:A multiplier 53 extracting a clock component being a reference signal used to match the synchronization of a reproduced clock outputted from a voltage controlled oscillator 7 is actuated by demodulation data inputted from an input terminal 1. On the other hand, a multiplier 3 extracting the clock component from identification data obtained from eliminating fluctuation in the demodulation data with a D flip-flop 2 is provided and the clock component is directly inputted to a data terminal D of the D flip-flop 5 detecting out of synchronism of the reproduced clock.</p>
申请公布号 JPH05145535(A) 申请公布日期 1993.06.11
申请号 JP19910304898 申请日期 1991.11.20
申请人 TOSHIBA CORP 发明人 OI TOSHIHIKO
分类号 H04L7/00 主分类号 H04L7/00
代理机构 代理人
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