| 摘要 |
PURPOSE:To reduce the hardware quantity and to increase the operating speed of a multiplication circuit by improving the part where many partial product bit signals are added together for production of the signal that is inputted to a carry transmission type adder circuit and then omitting the correction terms of a code non-expanded correction arithmetic system. CONSTITUTION:An (8X8)-bit multiplication circuit which has the maximum value '4', for example, of the same level digit addition number is obtained with combination of the prescribed 3Pm and 4Pm circuits. Then the signal, that added '1' to the digit N of a higher place or each partial product for correction of codes is produced as a partial product bit signal of each corresponding digit. Then this signal is added to another partial product bit signal of the relevant digit and therefore a sum signal and a carry signal of each digit are produced. In this case, N means an integer of '2' or more. As a result, the hardware quantity is reduced and the operating speed is increased for the multiplication circuit. |
