Memory cell for first-in first-out semiconductor memory - has latch circuit with access gates provided by MOSFETs

摘要

The memory cell uses a latch circuit with a pair of cross-coupled complementary MOSFET inverters (5a,24a;5b,24b) and MOSFETs (3,4). These are coupled between the input (N10) of the latch circuit and a write bit line (WBL) and between the output (N20) of the latch circuit and a read bit line (RBL). The transistors (3,4) respond to signals along a write word line (WWL) and a read word line (RWL). Preferably, a write address decoder , receiving externally supplied write addresses, is used to select the write word line (WWL). A read address decoder similarly selects the read word line (RWL). ADVANTAGE - Allows high integration density by reducing number of required transistors.