发明名称 |
Method of constructing termination electrodes on yielded semiconductor die by visibly aligning the die pads through a transparent substrate |
摘要 |
A process for fabricating conductive bumps on the bond pads of yielded good die includes forming a transparent structure upon which a masking layer is formed, aligning yielded good die and attaching them to the masking layer, and attaching a backing material to the backside of the die for mechanical support. The transparent structure is then removed and fabrication of the bumps continued on the bond pads of the good die by conventional means.
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申请公布号 |
US5171712(A) |
申请公布日期 |
1992.12.15 |
申请号 |
US19910811755 |
申请日期 |
1991.12.20 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
WANG, TSING-CHOW;LIANG, LOUIS H. |
分类号 |
H01L21/60;H01L21/68;H01L23/485 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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