| 摘要 |
FR 9 87 014 A semiconductor memory device including a pair of bit lines (BL, ??) having relatively high stray capacitances (C1, C2), a word line (WL), and a memory cell (MCl) connected to the said bit lines and word line, selected by an address signal, and a restore circuit comprising a coupling/equalizing circuit (12) controlled by a BLR clock and a reference voltage generator (51), for quickly restoring the said bit lines. According to the present invention, the said reference voltage generator (51) comprises both static and dynamic current sources. The static current source consists of a small N MOS transistor (N52) operating as a resistor load, while the dynamic current source consists of at least one small P MOS transistor (P'53, ...), connected in parallel with the said N MOS transistor, and gated with a clock (BCC',...) derived from the said BLR clock, so that the said P MOS transistor is turned ON during the restore time. An additional N device (N54) may be inserted between the reference line (RL) and ground (GND). The improved reference voltage of the present invention significantly reduces both consumed silicon area and restore time. |
