Stacked etch fabrication of cross-point EPROM arrays.

摘要

Two process flows are disclosed for the stacked etch fabrication of an EPROM array that utilizes cross-point cells with internal access transistors. In each process flow, the edges of the polysilicon 1 floating gates parallel to the polysilicon 2 word line are self-aligned to the word line, eliminating parasitic polysilicon 2 transistors and process requirements for coping with such transistors. <IMAGE>