| 摘要 |
<p>PURPOSE:To easily logically design by preparing a plurality of flip-flops of the same logic, and automatically replacing them. CONSTITUTION:Flip-flops (FF) 5, 6 are disposed and wired by using the same FFs 5, 6. Then, a delay simulation is executed, and if a difference of a delay time from a point (a) to a C input of the FF 6 and a delay time from the point (a) to a D input of the FF 6 does not satisfy a holding time of the FF 6, the FF 6 is automatically replaced with an FF 2. That is, disposition and wiring of a logic block is once performed, and a delay simulation added with an actual wiring length from the wiring result is executed. Thus, the delay time is not estimated redundantly at the upstream of a design, but a logical design can be easily performed.</p> |
