| 摘要 |
A binary parallel adders includes amplifiers (U1,U2) having the number corresponding to the sum output of N bits and a carry generation from the result of the adding process, an augend input synapse group for commonly connecting a power voltage to an input line of each amplifier with the connecting-weight value corresponding to each bit value of the augend input of N bits, an addend input synapse group for commonly connecting a power voltage to an input line of each amplifier with the connecting-weight value corresponding to each bit value of the binary addend of N bits, and a carry input synapse group for commonly connecting a power voltage to an input line of each amplifier with the connecting-weight value of a reference weighting value corresponding to the carry input.
|
