| 摘要 |
<p>PURPOSE: To obtain a fast memory operation by adding second equalization transistors and also using one set of a breed current device for all paired bit lines to reduce bit line capacitances. CONSTITUTION: When gates of precharge transistors N6, N7 are connected to the input node 36 of a precharge signal BLPRE, when the BLPRE is a high logical level, bit lines 26, 28 are precharged with the potential of not larger than a power source potential VCC. When gates of equalization transistors P4, P5 are connected to the input node 38 of a complementary equalization BLEQ, when signals are activated lows, the signal are stabilized at equalization voltages. Nodes 36, 38, 40 are shared with other precharges and equalization circuits to be connected to additional paired bit lines. Thus, since only one breed current device 41a is required for all static random access memory arrays, bit line capacitances are reduced.</p> |
