The circuit includes a manually operating means (3) for operating the circuit by manually manipulating switches. A preset signal generating means (5) generates pre-set signals at the instant when the manually operating means (3) is set, and a processor interface means (9) receives clock control data from a processor. A counter means (7) receives signals from the preset signal generating means and from the processor interface means to pre-set them by using the clock control data of the processor as the initial value. Upper and lower switches (1)(2) generate signals to increment or decrement the clock control data of the counter means, and a latching means (8) latches the clock control data of the counter means.
申请公布号
KR920005597(B1)
申请公布日期
1992.07.09
申请号
KR19890013187
申请日期
1989.09.12
申请人
KOREA TELECOMMUNICATION CORP.;KOREA ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人
JU, BOM - SUN;LEE, CHANG - MUN;LEE, JONG - HUI;KIM, OK - HUI