| 摘要 |
<p>PURPOSE:To improve defect rate by complimentarily storing the data of one bit at first and second transistors for storage, and reading it by differentials. CONSTITUTION:The data of one bit is complimentarily store in first and second transistors 11, 12 for storage through first and second transistors 13, 14 for selection. The gate of the transistor 11 for storage is connected to the source of the transistor 12 for storage, and is connected to a write-in circuit 20. Also, the control gate of the transistor 12 for storage is connected to the source of the transistor 11 for recording, and connected to a erase voltage supply line ERL. Then, by reading the storage data by differentials with the first and second transistors 13, 14 for selection, the life of the memory cell can be improved, and the defect of one of the first and second transistors 11, 12 for storage can be relieved by the other transistor. Thus, the rate of defect can be reduced.</p> |
