发明名称 A/D CONVERSION SYSTEM FOR DATA SIGNAL
摘要 PURPOSE:To exclude effect of noise by fetching data for plural number of times for each bit, comparing a binary digital value of each times and deciding 1 or 0 in binary value through majority decision. CONSTITUTION:As the method of the hardware, a majority decision circuit 8 which decides a polarity depending on a difference between negative and positive values by means of a counter is provided to the hardware. As the method of the software, majority decision of plural fetch results of outputs of A/D conversion from a waveform shaping output and serial/parallel data conversion are implemented based on the software of a CPU 7 processing a data signal to simplify the circuit constitution. Thus, effect of noise is eliminated.
申请公布号 JPH04123550(A) 申请公布日期 1992.04.23
申请号 JP19900244686 申请日期 1990.09.14
申请人 YAESU MUSEN CO LTD 发明人 KAMEI MANABU
分类号 H04L27/14;H04L25/08;H04L27/156 主分类号 H04L27/14
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