EINRICHTUNG ZUR SERIELLEN UEBERTRAGUNG VON DIGITALEN MESSWERTEN WENIGSTENS EINES MESSWERTWANDLERS.

摘要

Between a clock circuit (TGE) and a parallel-series changeover input (PSU) of a parallel-serial shift register (PSS), there is provided a clock-controlled sequential circuit (TSS1). The circuit has a serial-serial shift register (SSS) with a differencing circuit (DG) and an internal clock (TG1), or a series-parallel shift register with a logic circuit downstream of it and an internal clock. The serial-serial register has two flip-flops (FF1,FF2) clocked from the internal clock and receiving reset inputs from the difference circuit (DG). The serial output is connected to the changeover input (PSU). The series-parallel embodiment is coupled by a NOR-gate to the changeover input.