| 摘要 |
An operation of a CPU is defined by a predetermined clock. An image memory stores in or read-out image data to be displayed. A display controller connects between the CPU and the image memory, and receives a command from the CPU during an access period set by time-dividing a display period and for controlling a write or read operation of the image data with respect to the image memory. A timing signal generator generates a reference pulse for representing a relationship between the clock for defining the operation of the CPU and the access period. An operation state detector receives the reference pulse generated by the timing signal generator and an access control signal output from the CPU, and detects a state of the CPU with respect to the access period. A wait signal generator generates a wait signal to the CPU, in accordance with a detection result from the operation state detector.
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