| 摘要 |
PURPOSE:To enable the content of a memory loop of a memory cell to be easily inverted and a write operation to be executed more easily a compared with a conventional one by a method wherein a resistive element or a resistive element connected to a transistor in parallel is inserted between the ground terminal of an inverter circuit which forms the memory loop of a memory cell and the ground terminal of a chip. CONSTITUTION:The ON-state resistances of an NMOS transistor and a PMOS transistor are represented by R and 2R. Provided that the resistance of a resistive element 4 is represented by Rg and an NMOS transistor 1b and a PMOS transistor 2a are not provided, the potential of a nodal point A is represented by a formula, VDDX(R+ Rg)/(3R+Rg), conforming to voltage division by resistors and becomes higher than VDD/3 in a conventional circuit. The potential of a nodal point B is equal to VDD/2. As the potential of the nodal point A becomes higher than that in a conventional circuit, the NMOS transistor 1b is lessened in ON-state resistance. Therefore, the potential of the nodal point B becomes lower than usual. By this setup, the PMOS transistor 2a is made to decrease in ON-state resistance. As mentioned above, the potential of the nodal point A becomes higher than that of the nodal point B more easily than usual, so that a normal write operation cab be expected. |
