发明名称 HEADER DRIVING TYPE SWITCH
摘要 <p>PURPOSE:To reduce the reduction of throughput caused by the read/write of a RAM by providing a shared memory divided into plural independently operatable memory blocks, address control part, input/output line correspondence part and arbiter. CONSTITUTION:A common RAM 101 is divided into plural blocks (into two blocks in this case), and attending on the division, an arbiter 105 and an idle address memory 106 are provided at every block. In the front step of each RAM 101, a multiplexing part 109 is provided to multiplex a write data and before and behind the idle address memory 106, a selector part 108 and a distribution part 107 are provided. The imbalance of simultaneous access to the RAM between a read side and a write side caused by the difference of the state of a requirement from an input/output part to each arbiter is absorbed by the arbiter with an arbitrating function for controlling the read/write access allocation of the arbiter.</p>
申请公布号 JPH0447828(A) 申请公布日期 1992.02.18
申请号 JP19900157189 申请日期 1990.06.15
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KAI HIDENORI;YAMADA HIROKI
分类号 H04Q3/52 主分类号 H04Q3/52
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