发明名称 DELAY SYNCHRONIZING LOOP CIRCUIT
摘要 PURPOSE:To fix a voltage controlled oscillator to a prescribed voltage and to quicken the synchronization locking by bringing the state to a synchronizing loop control range deviation state when any of a correlation between a reception signal and two adjacent receiver PN code series is a prescribed threshold level or below. CONSTITUTION:A transmission data modulated by a PN code series (CS) is used as a reception signal Sr, a correlation between a receiver side code equal to the series CS and the signal Sr is obtained by two multiplier sections 1, 2 and envelope detectors 3, 4. Correlation outputs (1), (2) of the detectors 3, 4 are fed to a subtractor 6 and a phase comparator section 9 and when any of the outputs (1), (2) reaches a threshold level being zero and an offset or below, the state is discriminated to be a synchronizing loop control range deviation state, and a selector 10 selects a prescribed voltage +V controlling a voltage controlled oscillator VCO 7 in place of an output of a loop filter 6. Thus, the synchronization locking is quickened without deviating the control range of the delay synchronizing loop.
申请公布号 JPH03258131(A) 申请公布日期 1991.11.18
申请号 JP19900057713 申请日期 1990.03.08
申请人 FUJITSU LTD 发明人 IIZUKA NOBORU;YAMASHITA ATSUSHI;MATSUYAMA KOJI
分类号 H04J13/00;H04B1/7085;H04L7/00 主分类号 H04J13/00
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