| 摘要 |
PURPOSE:To attain smooth clock switching without a large fluctuation in the oscillating frequency by implementing the switching of self-running and subsequent state of a dual loop type PLL circuit based on raw information representing the clock input interruption after the lapse of a proper time. CONSTITUTION:When the state of the presence of a data input is switched to the state of the absence thereof, in the case of sets of sharpness Q1, Q2 of 1st and 2nd clock intermediate frequency circuits 1, 2 being in the state of Q1>Q2, the relation of times T1, T2 from the data input interruption till the loss of the clock is T1>T2. On the other hand, when the relation of T2+T3<=T1 is satisfied, where T3 is a delay time when clock interruption is detected by a clock input interruption detection circuit 4 and till the output of a selector 7 is switched into an output of a reference voltage generating circuit 5, the input voltage to a voltage controlled oscillator 14 in a dual loop type PLL(Phase Locked Loop) circuit 6 is largely fluctuated. The self-running state is transited smoothly without largely fluctuating the oscillating frequency. |
