| 摘要 |
<p>PURPOSE:To obtain the same effect with the equivalent equalization of signal line length at the input terminal of a receiving circuit, by supplying differential inputs to a driving circuit which generates a complementary clock, a terminating circuit for reflection prevention, and the receiving circuit. CONSTITUTION:When three receving circuits are provided, the lengths of signal lines 12 and 13 are so determined that l1=l1' and l2=l2', where the line lengths between positive inputs of registers 20 and 21, and 21 and 22 are l1 and l2, and those between negative inputs of the registers 21 and 20, and 22 and 21 are l1' and l2'm. Then, a driving circuit 10 outputs a positive and a negative complementary clock signal, having a constant-gradient leading or trailing edge, to signal lines 12 and 13 by an input from a clock signal input line 11. A terminating circuit 30 has a resistance value equal to the characteristic impedance values of the signal lines 12 and 13 and terminates the signal lines 12 and 13 at a terminating voltage source VT.</p> |
