| 摘要 |
A random access memory (RAM) device capable of performing logic combinations of new and previously stored data in a single memory access cycle. In contrast to conventional RAM data combination sequences, which involve a succession of read-modify-write cycles, the present architecture implements logical combinations of new RAM data with old RAM data during a single access cycle. In a preferred arrangement, decoding logic combines the new data with mode select signals to generate a set of FORCE 1, FORCE 0, COMP and NOOP control signals. The control signals regulate the bit line sense amplifier and logic to allow direct interaction with the bit line data during RAM addressing. The invention is particularly useful in graphic video display systems frame buffers where rapid pattern changes are difficult to implement using moderate speed and cost RAM devices.
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