| 摘要 |
If the period of a horizontal synchronizing signal component output from a synchronizing separator circuit differs from a predetermined horizontal trace period, a decision-making circuit determines that a channel with no signal has been received, making high the frequency of a clock for generation of a write address. If the period of the horizontal synchronizing signal component equals the predetermined horizontal trace period, the decision-making circuit makes low the frequency of a clock for generation of a write address. Accordingly, in a multiple-channel picture display mode, in the case of the reception of a channel with no signal, writing for one horizontal trace period is completed in a shorter time than writing in the case of reception of a channel with a signal. The received signal of each channel is correctly written into a picture memory in each horizontal trace period irrespective of variations in the dispersion of the period of the horizontal synchronizing signal component. Accordingly, it is possible to eliminate the problem that, as in the prior art, the next horizontal synchronizing signal component appears during the current write period to cause multiple-channel pictures to be displayed at locations offset from corresponding display frames. It is, therefore, possible to correctly identify the picture information of each channel with a signal.
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