发明名称
摘要 PURPOSE:To omit an instruction exclusive for bit decision of data on a RAM and to simplify an instruction system by executing a prescribed instruction immediately before the execution of a bit decision instruction of an accumulator, therefore deciding the bit of the RAM data. CONSTITUTION:When a bit decision instruction of an accumulator is executed, an instruction decoder 16 delivers a control signal ACTAL to control a selection circuit 15. At the same time, an instruction (RAM bit decision instruction) to be executed before the bit decision instruction of the accumulator is executed. Then the decoder 16 delivers a control signal BTAL and a TMB signal. The signal TMB is applied to a delay circuit 18 and delayed consecutively until the execution is through with a RAM bit decision instruction. The output of the circuit 18 is applied to a gate circuit 19. When the bit decision instruction of the accumulator is executed independently, the signal ACTAL is applied to the circuit 15. However the signal ACTAL is cut off by the circuit 19 with the output of the circuit 18 if the bit decision instruction is executed after the RAM bit decision instruction.
申请公布号 JPH0255809(B2) 申请公布日期 1990.11.28
申请号 JP19840084878 申请日期 1984.04.25
申请人 SANYO ELECTRIC CO 发明人 TAKAHASHI ISAO
分类号 G06F7/00;G06F9/30;G06F9/308 主分类号 G06F7/00
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