| 摘要 |
PURPOSE:To improve the integration of a vertical transistor device by laminating the prescribed number of P type layers and N type layers in a thicknesswise direction in the prescribed sequence at both sides of a V-shaped groove on the surface of an Si substrate, thereby vertically arranging a plurality of devices of different operating states. CONSTITUTION:Many P type layers 2 and N type layers 3 are laminated on the surface of an N type Si substrate 1, and a V-shaped groove 4 which crosses the center between the layers 2 and 3 is formed. Subsequently, the groove and the substrate are covered with an SiO2 film 5, and a gate electrode 6 is formed on the surface of the groove. When MOSFETs of different operating states are formed at the right and left sides of the groove in this case and suitably wired, a C-MOS circuit can be formed, and can be vertically formed. Accordingly, the degree of integration can be improved. |
