| 摘要 |
PURPOSE:To decrease a quantization error of an input signal enough to use it even for a high-precision control system by adding the detection output of a counter means to information detected on the basis of a machine cycle. CONSTITUTION:While a control signal CTL from a microcomputer 1 is at a level H, the input of a signal A is held in readiness. At this time, the output of an inverter 10 is at a level L and the output of an NAND8 is at the level H. On the other hand, the input signal A is at the level L, so a counter 6 is reset. Once the input signal A is inverted to the level H, a request for interruption is sent out to the microcomputer 1, but the microcomputer 1 detects that a specific time later. During this period, the counter 6 counts a high-speed clock signal CPH. Therefore, the counted value of the counter 6 is inputted simultaneously with the fetch of the signal A, and consequently its detection error is suppressed within one cycle of the high-speed clock signal CPH. |
