| 摘要 |
PURPOSE:To reduce a parasitic resistance, to lower a capacitance between a drain and a base and to eliminate a thermal runaway by dividing a base region including a channel into a high-concentration layer and a low- concentration layer. CONSTITUTION:Polysilicon 1 to be used as a gate and a gate insulating film 2 are formed. A P<+> well 3 is formed in advance. After a P<->-base low- concentration layer 4 has been formed by ion implantation and thrust, a P-base high-concentration layer 5 is formed. A source 6, an interlayer insulating film 7 and a hole 8 for contact use are formed; after that, a source electrode 9 is evaporated; a vertical-type MOSFET whose base is composed of the high- concentration layer 5 and the low-concentration layer 4 can be obtained. By this setup, a parasitic resistance is reduced; a capacitance between a drain and the base is lowered; a thermal runaway is eliminated. |
