发明名称 BUS TIMING CONTROL CIRCUIT
摘要 <p>PURPOSE:To allow an input/output card operated by an input/output clock being different from a CPU clock to coexist by the same system by synchronizing a selected clock and the CPU clock. CONSTITUTION:When it is recognized that a card of an extended slot is brought to access, one of READY input signals A-C becomes inactive, and by which clock it is operated is informed to a system board. By a fall of its READY input signals A-C, the clock which is selected through a gate is outputted as an input/output clock to an extended bus. Also, the READY signal sets an MPU to WAIT state, the card of the extended slot secures a set-up time and makes the READY signal active, and the selected clock and a CPU clock are synchronized. That is, flip-flops 60, 70 contrive the synchronization of an input/output clock (I/O CLK) and the CPUCLK. In such a way, the card which is designed by a flow or quick input/output clock can be allowed to coexist on the same system.</p>
申请公布号 JPH01248219(A) 申请公布日期 1989.10.03
申请号 JP19880076927 申请日期 1988.03.30
申请人 TOSHIBA CORP 发明人 SHIMOMURA TSUTOMU
分类号 G06F13/42;G06F1/04;G06F1/06 主分类号 G06F13/42
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