| 摘要 |
A field effect transistor has its drain and source regions connected between one of the two supply pads of an operative integrated circuit, the gate of the field effect transistor being connected to the other pad such that the gate is negatively biased during reverse battery to prevent current flow through the circuit in this condition and, hence, to prevent destruction of the circuit. The FET is sized to have minimal voltage drop during normal, forward battery operation of the circuit. The FET can be implemented as either an N-channel or a P-channel device.
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