| 摘要 |
A frame synchronizing signal detecting circuit detects a frame synchronizing signal in a video signal. When the frame synchronizing signal is not detected by the frame synchronizing signal detecting circuit, a clamp level switching circuit is responsive to a switching signal from a timer circuit for generating alternately an upper clamp potential V+ and a lower clamp potential V-. When the frame synchronizing signal is detected by the frame synchronizing signal detecting circuit, the clamp level switching circuit generates a normal clamp potential V0. A clamping pulse generating circuit is responsive to an output from the frame synchronizing signal detecting circuit for generating a clamping pulse. A clamping circuit is responsive to the clamping pulse for clamping an analogue video signal at the clamp potentials V0, V+ or V- from the clamp level switching circuit.
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