A Semiconductor memory operating with a low peak current.

摘要

A semiconductor memory including memory cells each connected to one of a first set of lines for selecting column address signal and to one of a second set of lines for selecting a row address signal, decoder responsive to address signals and a switching signal for producing a column address selecting signal and switching control signal, sense amplifier drive control circuit responsive to the column address selecting signal for producing sense amplifier driving signals, sense amplifier circuit responsive to the sense amplifier driving signals and the column address signal for amplifying the column address signal in response to the sense amplifier driving signals, and switching device responsive to the amplified sense amplifier driving signals and the switching control signal for outputing the amplified sense amplifier driving signals to data lines. In this semiconductor memory, since the sense amplifier driving current can be made so small, the power supply peak current can be considerably reduced.