| 摘要 |
PURPOSE:To improve the response of synchronization control of a clock pulse by holding a control signal just before when a phase difference between a horizontal synchronizing signal and a clock pulse is larger than a prescribed range. CONSTITUTION:The phase of a horizontal synchronizing signal HS of a TV signal and that of a reference signal (d) being the frequency-division of the clock pulse from the pulse generating circuit 7 are compared by a phase comparator 3 and its output controls the oscillating frequency of the voltage controlled oscillator 6. When the frequency of the clock pulse rises and the phase difference with the signal HS exceeds a prescribed range, an output is caused in a NAND gate 9, a FF circuit 10 is set and a holding circuit 4 holds the control signal just before. Then the oscillated frequency of the oscillator 6 is decreased by a negative control signal and when the frequency reaches a prescribed range, the gate 8 is outputted to release the holding state of the circuit 4. Thus, the response of the synchronizing control of the clock pulse is improved. |
