FRAME SYNCHRONIZING SYSTEM

摘要

PURPOSE:To reduce the operating speed of a logic element by applying serial/ parallel conversion to a high-order group input signal at a prescribed speed and detecting a synchronizing pattern in parallel simultaneously with respect to a prescribed bit number subjected to parallel conversion. CONSTITUTION:Pattern detection circuits 3-8 are constituted as 1-input NAND gates. Then the frame synchronizing pattern is detected while the PCM input signal is once expanded in parallel at an optional phase in an optional parallel number M satisfying the condition of N