发明名称 Control circuit for calibrating a delay line
摘要 Control circuit for calibrating a delay line for a television receiver. The delay line contains series-connected all-pass sections of at least 2nd-order, the inductances of which are replaced by gyrators to which capacitances are connected. During at least one line of the vertical blanking period, the delay line is included into a phase-lock loop for comparison with a line-frequency signal in order to control the delay time of the all-pass sections.
申请公布号 US4805021(A) 申请公布日期 1989.02.14
申请号 US19860939385 申请日期 1986.12.08
申请人 U.S. PHILIPS CORPORATION 发明人 HARLOS, HARTMUT;JUHNKE, KLAUS G. H.;KELTING, PETER
分类号 H04N5/953;H03H11/26;H04N5/14;H04N9/64;H04N9/77;(IPC1-7):H04N5/14 主分类号 H04N5/953
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