发明名称 CLOCK REGENERATING CIRCUIT
摘要 PURPOSE:To process a demodulated base band signal digitally without any adjustment even if a clock frequency varies by generating a clock whose phase difference is held at a specific value by a clock generating means by using a control signal corresponding to the phase difference between the zero cross point of the demodulated base band signal and the change point of the clock. CONSTITUTION:A phase comparing means 7 extracts the output corresponding to the phase difference between the zero cross point of the demodulated base band signal and the change point of the clock and a control signal generating means 8 generates a control signal by using said output. then the frequency dividing operation of the clock generating means 9 for a reference clock is controlled with the control signal to generate the clock whose phase difference is held at the specific value. When the clock frequency varies, the frequency dividing operation corresponding to the variation is performed to perform the digital processing of the demodulated base band signal without any adjustment.
申请公布号 JPS63308412(A) 申请公布日期 1988.12.15
申请号 JP19870144266 申请日期 1987.06.10
申请人 FUJITSU LTD 发明人 TOZAWA YOSHIHARU;FUJIOKI ICHIROU
分类号 H03L7/095;H03L7/08 主分类号 H03L7/095
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