| 摘要 |
PURPOSE:To simplify the circuit constitution and to attain short time access by providing a requester sending a bus right request signal to an arbiter arbitrating the bus right of the system so as to arbitrate the bus right of on internal bus. CONSTITUTION:When a master/slave 11(M3) generates a transfer request (at this point of time, access to a bus (b) or (c) is not clear), a bus right request signal is given to an arbiter CO of a system bus 1 via a requester 14 in a card C3. When a bus right of a system bus 1 is recognized in the M3, the requester 14 of the card C3 occupies the system bus 1 after the present bus cycle is finished. Then the M3 uses the internal bus B3 to start the actual access. When it is an access to the bus (b), the system bus 1 is being occupied, and if the access is directed to the bus (c), the system bus 1 is released. The distinguishment between the buses (b) and (c) is implemented by a decoder 13 and it is delivered to the requester 14. Thus, the circuit constitution is simplified and the access time is decreased.
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