| 摘要 |
PURPOSE:To shorten the delay time of a signal, and to prevent the generation of a skew by forming a signal wiring channel for shaping signal wirings connecting a plurality of circuits formed, holding a memory section onto the memory section. CONSTITUTION:Input/output circuit sections 2 are provided in the peripheral section of a semiconductor chip 1 such as a silicon chip in a memory LSI having a logic. There is also provided memory sections 3 such as RAMs consisting of memory cell arrays composed of a large number of memory cells. The input/ output circuit sections 2 and said logic sections 3 are connected by signal wirings 5, signal wiring channels SC are shaped onto the memory sections 3, and these signal wirings 5 are formed onto the signal wiring channels SC. Consequently, the input/output circuit sections 2 and a logic section 4 can be connected by the signal wirings 5 without bypassing the memory sections 3. Accordingly, the signal wirings 5 can be made shortest, and the delay time of signals is shortened, thus increasing the working speed of the LSI. |
