发明名称 |
Circuit for calculating the discrete Fourier transform |
摘要 |
A circuit for calculating the discrete Fourier transform which includes a multiplier, two adders for effecting the calculation of the discrete Fourier transform while describing a butterfly data path, and address processors which supply the multiplier and adders with continuous data under the control of a synchronization clock. To accelerate the calculations, the processor has a memory for reducing the data access time. This memory is divided into two parts, each of which alternately plays the role of calculation memory and input/output memory for the transfer of data with a memory external to the processor.
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申请公布号 |
US4787055(A) |
申请公布日期 |
1988.11.22 |
申请号 |
US19850755278 |
申请日期 |
1985.07.15 |
申请人 |
THOMSON-CSF |
发明人 |
BERGEON, GERARD;LEGENDRE, CLAUDE;MULLER, MARC;CROS, PHILIPPE;LEMAIRE, JEAN-LOUIS |
分类号 |
G06F17/14;(IPC1-7):G06F7/34 |
主分类号 |
G06F17/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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