| 摘要 |
<p>PURPOSE:To preclude malfunction among central arithmetic processors and to improve the reliability of a system by using the bus request response signal of a central arithmetic processor and a delay circuit when a reset signal is sent out to other different central arithmetic processors. CONSTITUTION:A CPU 1 is reset with the reset signal (S.RESET) of the system and begins to operate and then a signal E.HAK is sent out to generate necessary reset conditions in a CPU 2 by the delay circuit 1 and a gate 2, so that they are sent out as the reset signal of the CPU 2. Consequently, a CPU which requires clock synchronism type resetting is utilized as the CPU 1 to securely reset the CPU 2 and the start of the operation of the CPU 1 is confirmed from the signal E.HAK, so the reliability of the whole system is improved.</p> |
