| 摘要 |
PURPOSE:To attain the simultaneous input/output of serial high speed data to a dynamic memory IC by providing a means to gate asynchronously a serial control clock respectively with a writing/reading clock gate from an external part. CONSTITUTION:Gate circuits 14 and 15 gate a serial control clock SC from an input terminal 2 by a writing clock gate CGW and a reading clock gate CGR from input terminals 3 and 4 and respective outputs are used as a clock SIC for fetching input data Din to a serial parallel converter 7 and a clock SOC for removing output data Dout from a parallel serial converter 8. Further, the SIC, SOC and SC of a reference are guided to a control circuit 16 to control data transfer at the section of an address generating 18, an SP converter 7, a PS converter 8, input output data registers 9 and 10 and a memory cell array 11 and the data transfer among respective ones is wholly synchronized to the SC.
|
