ENTKOPPLUNGSKONDENSATOR FUER SCHALTUNGSPACKUNGEN MIT OBERFLAECHENMONTIERTEN KONTAKTSTIFTLOSEN CHIPTRAEGERN, OBERFLAECHENMONTIERTEN CHIPTRAEGERN MIT KONTAKTSTIFTEN UND FUER SCHALTUNGSPACKUNGEN MIT KONTAKTSTIFTRASTER

摘要

A decoupling capacitor (16) incorporates at least one multilayer capacitive element 132 and utilizes as terminals metallized dielectric (e.g., ceramic) substrates 102, 116 rather than a pair of conductors. The decoupling capacitor of the present invention is specifically sized and configured so as to be either received in the space directly below the integrated circuit chip and between the downwardly extending pins of a PGA package or "leaded" chip carrier package or to be mounted directly over a "leadless" chip carrier package as in Figure 2. Each capacitive element is a multilayer arrangement with alternate electrodes interconnected by end terminations and the dielectric body preferably has an exposed electrode on opposite faces. Terminals are provided by metal layers (104, 118) on one or more ceramic housing parts (102, 116) that sandwich one or more capacitive elements (132). The latter can be surrounded by a spacer (128). Each terminal is provided with plural leads (26, 124) received in the holes of a pcb (20) or soldered to the terminals (18) of a surmounted or surmounting i/c, PGA or other i/c carrier. <IMAGE>