| 摘要 |
PURPOSE:To simultaneously read out an aimed bit specified at its address and its adjacent bits by simultaneously accessing plural memory mats by 1st and 2nd address selecting circuits and selecting an information bit with the specified address and information bits relating to the specified one. CONSTITUTION:A common column selecting signal is supplied to memory mats M00-M30 arranged in the X direction from one column decoder C-DCR0 and memory mats M00-M03 and column decoders C-DCR0-CDCR3 are also arranged in the Y direction. Plural memory mats M00-M33 are simultaneously accessed by the 1st address selecting circuit and the information bit with an address specified by an address specifying circuit and information bits relating to the aimed bit are selected by means of the 2nd address selecting circuit for specifying a prescribed memory mat out these memory mats M00-M33. Consequently, the aimed bit specified at its address and its adjacent bits can be simultaneously read out.
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