Universal asynchronous receiver-transmitter.

摘要

The UART can be selectably operated in a synchronous or an asynchronous mode. First-in, first-out (FIFO) registers (404,424) are provided for both the receiver and transmitter portions of the UART, and a parity error and special character recognizer unit (412) on the receive side flags characters when they are placed in the receive FIFO. Reception of a special character or one with a parity error is reported to the user via an interrupt mechanism (430). A random access memory (RAM)(413) with the special character recognizer stores user-supplied patterns which are recognized as special characters. User-accessible status and control registers (408) have bit positions which enable and control the enhanced functions of the UART while maintaining compatability with the industry standard.