发明名称 DATA SIGNAL DEMODULATION CIRCUIT
摘要 PURPOSE:To easily set a TTL level by impressing a reproduced FM video signal directly to the data input terminal of a D type flip flop and a reproduced FM video signal to a clock input terminal by delaying by a prescribed period and extracting the output of the D type flip flop only by the prescribed line of a vertical retrace line period to conduct out a data signal. CONSTITUTION:The reproduced FM video signal is directly impressed to the data input terminal of the D type flip flop 6 and the reproduced FM video signal delayed by the prescribe period is impressed to the clock input terminal of the D type flip flop 6, a reproduced horizontal synchronizing signal is counted by a gate control means 9 to form a gate control signal at a position where the data signal in the vertical return line period of the reproduced FM video signal is written. A gate means 7 controls the transmission of the output of the D type flip flop by the gate control signal and conducts out said data signal. Thereby, the data signal of the TTL level is directly obtained from the D type flip flop without converting to the TTL level in a complicate analog circuit.
申请公布号 JPS63121180(A) 申请公布日期 1988.05.25
申请号 JP19860265814 申请日期 1986.11.07
申请人 SANYO ELECTRIC CO LTD 发明人 ASAHARA TORU
分类号 H04N5/93;G11B20/10;G11B27/10 主分类号 H04N5/93
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