| 摘要 |
<p>PURPOSE:To erase clutter while a target signal is retained, by providing a delay element between a complex number multiplier and a load calculation means and shifting an input signal group and a range bin number of load. CONSTITUTION:Relay elements 19a-19c are provided between complex number multipliers 2a-2c and a load calculation means 5 and, when input signals UK(1)-UK(3) having a range bin number of K are transmitted to the multipliers 2a-2c, the loads applied of the multipliers 2 are not aK(1)-aK(3) but become aK-1(1)-aK-1(3) by the elements 19. The output signal vK of a complex adder 3 becomes a signal obtained by respectively adding the products of the outputs of the elements 19 and the output of a memory 1 and the output signal YK of a complex subtractor 4 becomes UK(4)-vK. A load calculation means 5 forms loads aK(1)-aK(3) using input signal groups UK(1)-UK(4) but said loads are used with respect to input signal groups UK+1(1)-UK+1(4) having a range bin number K+1. As mentioned above, by shifting the input signal groups and the range bin numbers of the loads, clutter can be erased while a target signal is retained.</p> |
