| 摘要 |
PURPOSE:To easily synchronize a clock with high accuracy by providing a discrimination means so as to advance or retard a multiplied output of a 2nd multiplication means in discriminating phase lag or lead. CONSTITUTION:The oscillated output of an oscillator 1 is multiplied by a multiplication circuit group 3 and a master clock 11 is outputted. The oscillated output of an oscillator 2 at the same period of that of the oscillator 1 is multiplied by a multiplier circuit group 4 and a slave clock 12 is outputted. In discriminating that the clock 12 is advance from the clock 11, the discrimination circuit 5 outputs an instruction signal 13 to a multiplier circuit 6n to apply synchronizing control. That is, the pulse of a signal 15 is counted excessively by one period, the pulse signal 12 is sent at the 11th period to prolong the period of the signal 12 by one period of a signal 15. In discriminating the delay, an instruction signal 14 is sent to the circuit 6n to give fewer count of the signal pulse 15 by one period conversely, the pulse signal 12 is sent at the 9th period to decrease the period of the signal 12 by one period of the signal 15. |
