| 摘要 |
PURPOSE:To suppress surely generation of consecutive 0s by adding 1 bit to an input signal and using this bit as a complementary code and a frame synchronism bit of a preceding bit to simplify a timing circuit. CONSTITUTION:A parallel data input (a) is subjected to scrambling with a PN series being an output of a PN (pseudo random) pattern generating section 22 at an exclusive OR circuit 22 and converted into a random code. The least significant bit among N parallel outputs (c), and a frame synchronizing signal (f) are inputted to an exclusive OR circuit 23, where a code of the same sign is formed when the frame synchronizing bit is detected and an inverted code is formed when not, and signals g,c are outputted as a serial signal by a parallel-serial converting section 24. Thus a timing control circuit 25 has only to form a clock (e) for serial data being an integral number of multiple of (N+1) times the word clock (d) and the frame synchronizing signal (f) and further, since a 1-bit complementary code is inserted, the number of consecutive 0s is specified surely. |
