| 摘要 |
Arbitration units (A-0, A-1 etc.) associated with respective processors U-0, U-1 etc. are connected to an arbitration bus (2) having pref. four unidirectional wires allotted to distribution of clock pulses (CLO-CL3). Signals indicating bus occupancy and restoration are conveyed by external lines (4,5), while the arbitration units (A) and processors (U) are connected by lines for requests (6), priority levels (7), request acceptances (8), error signals (9) and addressing (10). At a first stage the selected unit's age is set to zero and the ages of other units are incremented by 1 if they were lower, or remain unaltered if they were higher. At a second stage the highest priority level is selected, and at a third stage the most aged unit at that level. The next cycle then begins if the bus (1) is found to be free. |
