| 摘要 |
PURPOSE:To prevent an output pulse from being absent even if a control signal is inputted asynchronously and even if there is internal delay by applying the control signal to a tri-state output circuit through a delay circuit. CONSTITUTION:When the control signal CS varies in level at a point t1 of time, a flip-flop fetches data at the rise of the clock, so the L level of the CS is fetched at the rise of a pulse (a) of IS appearing first after the point t1 and its Q output CS' is held at the L level. A tri-state buffer 20, therefore, becomes high in impedance and a pulse (a) does not generate an output pulse OS. When the control signal CS goes up to H at a point t2 of time, it is fetched at the rise of a next pulse (b) and the Q output CS' of the flip-flop 10a goes up to H, and consequently the tri-state output circuit 20 serves as a normal buffer and restarts outputting operation with the pulse (b). Thus, the output OS is a pulse train which has no absent pulse from the pulse (a) to immediately before the pulse (b).
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