| 摘要 |
PURPOSE:To attain an extremely faster transformation of a real number value expressed internally into a binary integer, compared with the case in a microcomputer, by providing a data latch, an exponent comparator, a shift frequency arithmetic circuit and a shift register. CONSTITUTION:The '1' is added to the highest place of beta via an external circuit and the positional notation is decided for decimal points by alpha of an exponent part. In such case, 127<=alpha<=143 (0<=alpha'<=16) is satisfied. If the value of alpha is not coincident with the relevant conditions, that is, a real number R is excessive or equal to the decimal value, an error signal is delivered from an exponent comparator 3. While the shift signals are delivered to a shift register 6 in the maximum frequency (n)=alpha1-alpha in case the value of alpha is coincident with said conditions. Then a mantissa beta is transferred from a data latch 2 to the register 6 and at the same time '1' is added to the highest digit through an MSB circuit 7 to obtain beta' in a state T0. Thus the digits higher than a decimal point remain by shifts of (n) times; while the digits lower than the decimal point are set under the state of shift-out Tn. |
