| 摘要 |
PURPOSE:To curtail a manufacturing process by a method wherein, after a plurality of elements are formed on a semiconductor substrate by electrical isolation, openings for electrodes are provided in an insulating layer formed on the surfaces of the elements, a wiring layer is so connected as to cover the openings, and then the wiring layer is etched to be in a prescribed pattern with the elements made inactive partially. CONSTITUTION:All MOS transistors to be connected to intersecting points of a polysilicon wiring layer 2 and an aluminum wiring layer 1 are prepared in an active state. Then, an insulating layer 6 is formed on the surface of a semiconductor substrate 10 whereon these MOS transistors are constructed, and openings 7 are provided in all of the source-drain portions of the MOS transistors which are ROM components, so as to form a structure enabling the leading-out of electrodes. Then, aluminum, an aluminum alloy or the like is connected on the whole surface of the semiconducto substrate so that it covers the openings. Subsequently, a conductive wiring layer formed by this connection is patterned with a part thereof left behind so that it extends on the surface of the insulating layer 6 to short-circuit between sources and drains in in the portions of MOS transistors to be made inactive. By this method, a time required from alteration to completion of a final product can be curtailed. |
